HyperSilicon announced to become the agent of Bluepearl’s Visual Verification™ Suite!

Wuxi, China, March 25, 2022 – HyperSilicon Co., Ltd., a leading supplier of FPGA-based prototyping and emulation tools and solutions, announced to become the agent of Bluepearl's Visual Verification™ Suite!

Visual Verification™ Suite has 6 main components: HDL Creator™, Analyze RTL™, Clock Domain Crossing (CDC), Management Dashboard, Automatic SDC Generation, Advanced Clock Environment (ACE). The Visual Verification Suite is proven softwares for high reliability design which enables engineers to rapidly locate and correct errors, early in the design cycle and finds subtle bugs that can be missed by even the most experienced designers.


Brief introduction of Visual Verification™ Suite

HDL Creator™

HDL Creator™ provides real-time syntax and style code checking inside an intuitive, easy-to-use full featured editor. Unlike standard editors, HDL Creator™ provides advanced real-time file analysis to find and fix complex issues as you code, such as compilation dependencies and missing dependencies. In addition, HDL Creator provides advanced design views to help understand and debug as you code.

◆ Analyze RTL™

Analyze RTL™ provides RTL linting combined with a powerful debug environment with the industry’s fastest bug find/fix rate to quickly identify critical design issues, up front, streamlining simulation and synthesis while improving overall quality of results.

◆ Clock Domain Crossing (CDC)

Clock Domain Crossing Analysis solution comes with a complete set of CDC analyses, an Advanced Clock Environment (ACE) for solving the iterative and reactive CDC setup problem, and a comprehensive set of debugging tools.

 Management Dashboard

The Management Dashboard is built on top of the Visual Verification Suite’s industry standard SQL database. The tool monitors and logs messages, Clock Domain Crossings and waivers per run to provide real-time visibility into RTL verification progress.

 Automatic SDC

ASICs and FPGAs have many false paths and multi-cycle paths that implementation tools attempt to optimize to make timing goals. These paths can cause the critical paths to miss timing, and waste run time and system memory. Adding false path constraints frees up the synthesis tool to work only on necessary paths that will give better results for a design. Blue Pearl offers a way to automate false path generation that can be run after design changes. In a typical design, there may be a significant number of false paths or multi cycle paths. Passing all of them to synthesis or place & route can be very expensive and taxing to these tools. Blue Pearl’s smart SDC generation limits the number of exceptions generated, reads in critical paths information and accepts multiple formats.

◆ Advanced Clock Environment (ACE)

Blue Pearl Software’s ACE offers the capability to visualize clocks and asynchronous clock domain crossings in RTL designs to help users analyze their design for CDC metastability.

The Advanced Clock Environment (ACE) tool solves the iterative and reactive CDC setup problem experienced by designers. It is used before running a CDC analysis. With ACE, designers can clearly see if clocks are not in the intended domains and make corrections before in-depth CDC analysis.

About Blue Pearl 

Blue Pearl Software, Inc. provides products that check digital design issues at the functional or register transfer level (RTL) of the chip design flow. These issues include clock domain crossings (CDCs), synthesis vs. simulation mismatches, inadvertent latch generation, coding style and conventions, and basic linting, as well as verifying conformance with design standards such as DO-254, STARC, and RMM. Blue Pearl’s software is used by ASIC and FPGA designers early in the design flow on high-level functional design descriptions of an integrated circuit (IC), to develop higher quality RTL code, and can also automatically generate comprehensive and accurate timing constraints that significantly improve quality of results (QoR). Our customers can significantly reduce time to market, lower design costs, and make the design development schedule more predictable. Incorporating Blue Pearl’s products in the design flow is easy as all inputs and outputs are industry standards.

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Build a smarter design and verification EDA tool chain

HyperSilicon has been enthusiasm in accelerating SoC/ASIC design and verification for 13 years since 2009, Our mission is to help customers decrease the total-time-to-market of their products by providing the most advanced FPGA-based rapid prototyping system and high performance emulator, and being the agent of some advanced EDA tools and leading IPs/VIPs/Transactors. Visual Verification™ Suite is the next generation EDA solution for ASIC, IP and FPGA design and verification, the Suite augments our existing EDA tool to accelerate degital design development.