HyperSemu®-FPGA Based Testing
The growth of the scale and complexity of advanced IC design has brought great challenges to verification. FPGA based testing which runs large-scale RTL designs(DUT) in hardware delivers exponentially higher speed compared to simulators, benefiting from data processing parallelly. More and more development teams choose to deploy FPGA based testing tools to accelerate the verification of large-scale designs. HyperSemu®-FPGA Based Testing:HyperSemu® is an innovative high performance FPGA based testing for various types of FPGA design and system level algorithm design researched and developmented by HyperSilicon®. HyperSemu® delivers considerable testing capacity, Many intelligentized tools like hsSynth-the high-speed parallel compile solution, HyperProto-the partition tool, hsTrace-the DeepDebug tool and HyperSemu®-the emulation software are ready to shorten the time of RTL to bitstream and achieve higher debug productivity.

Acceleration Mode

Co-Simulation

Mainstream simulators like Modelsim, VCS, Questasim are supported to carry out co-simulation

Transaction based

A critical mode to accelerate testing which can achieve 20-1000 times acceleration

ICE Mode

Multiple types of connection between FPGAs and devices are supported for board level testing and acceleration

Matlab Mode

Create testing model and start a project quickly by Matlab

Hybrid Emulation

Dramatically shifts the development cycle to the left, as a byword for early and fast

Main Features

Simulation cannot be realized when the design scale is too large
HyperSemu® delivers considerable testing capacity which is selectable to macth the design
Simulators consume lots of time when dealing with a long testbench
Data will be processed quickly on the hardware and HyperSemu® can run dut and testbench in a fast speed
Simulators consume lots of time when a design consists of many softwares
Data will be processed quickly on the hardware and HyperSemu® can run dut and testbench in a fast speed
It takes lots of time to iterate an algorithm model
Matlab mode is supported to create testing model and start a project quickly
It is extremely difficult to connect the design of two completely different modules
ICE mode is supported to connect multiple types of FPGAs and devices for board level testing and acceleration
It is difficult to test IP and embedded softwares before the design is finalized
Hybrid emulation is supported to carry out early architecture optimization, early software development, actual hardware verification
Simulators consume to much time to inject faults
A large number of experienced faults can be quickly injected to improve the design reliability

Key Benefits

Design Language
Acceleration Mode
Testbench
Debug tool
Transactors
Capacity selectable
Click for Customized Solution

We will assess a solution of highest return on investment according to the your design as soon as possible.