The Blue Pearl Software, HDL Creator™ is ideal for developers coding both RTL and test benches who are seeking productivity, predictability and code quality for complex FPGAs, ASICs, and IP Designs.
HDL Creator™ provides real-time syntax and style code checking inside an intuitive, easy-to-use full featured editor. Unlike standard editors, HDL Creator™ provides advanced real-time file analysis to find and fix complex issues as you code, such as compilation dependencies and missing dependencies. In addition, HDL Creator™ provides advanced design views to help understand and debug as you code.
HDL Creator™ Smart Editor Available as both a stand-alone editor as well as integrated inside Blue Pearl's Visual Verification Suite, HDL Creator™ is ideal for all development teams regardless of their downstream verification environment.
The HDL Creator™ is a full-featured source code editor that provides real-time syntax and style checking during HDL code development. In addition to all the normal features you would expect from a code editor, HDL Creator™ provides over 2000 real time checks to streamline code development and avoid common coding mistakes that would result in downstream design iterations.
◆ Accelerates code development
◆ Visualize complex source code for efficient coding, reading and understanding of legacy code
◆ Ensures high quality code development
◆ Streamlines downstream development
◆ Block indentation (set to tabs or spaces)
◆ Auto-indent for new lines
◆ Folding (hide or view blocks of code)
◆ Syntax highlighting
◆ Brace matching
◆ Block commenting (Multiple styles)
◆ Choice of line end styles
◆ Graphics views
◆ Auto-analyze current file to show syntax issues
◆ Real-time syntax and coding style checks
Over 70 “Load Checks” can be enabled for Real-Time Analysis
Over 2000 Verilog and VHDL parsing
◆ Project and non-project modes
◆ Generation of PDF Documents
◆ Integration with simulators and downstream analysis
Visualize Your Project
HDL Creator™is not just an ordinary editor, as a smart editor it also provides real-time views that help you understand and verify issues as you code.
◆ Block View and module views
◆ Clock/Reset Domain schematic view
◆ Data flow schematic view
◆ Pre-Synthesis folder view
◆ Support for files external to the design
File view based on user defined libraries
Directory based view of file structure
Stand-Alone or Inside the Visual Verification Suite
HDL Creator™is provided as both a stand-alone HDL editor tool as well as integrated into Blue Pearl's Visual Verification suite.As a standalone editor, HDL Creator™is ideal for design teams that work closely with Verification teams, avoiding unnecessary design iteration between teams by catching common coding and style issues up front as you code! When used inside the Visual Verification Suite, additional analysis, views and integration are available that extend the HDL Creators capabilities streamlining HDL development.
The Blue Pearl Software Visual Verification Suite provides enhanced Lint, Debug, Clock Domain Crossing (CDC) and automated SDC generation flows to accelerate RTL Verification. Analyze RTL™ provides RTL linting combined with a powerful debug environment with the industry's fastest bug find/fix rate to quickly identify critical design issues, up front, streamlining simulation and synthesis while improving overall quality of results.
Modern ASICs, SoCs and FPGAs routinely have millions of gates with memories, transceivers, third party IP and processor cores. RTL issues can be time consuming and complex to debug in the lab and through simulations. To reduce verification and debug times, designers need tools that can identify problems quickly before simulation and synthesis, and definitely before spending time in the lab.
◆ Analyze RTL, accelerates RTL verification and debug:
◆ Fast and meaningful results with tool Setup Wizard
◆ Check IEEE Verilog/System Verilog & VHDL language specification compliance and syntax
◆ Configure checks along with standard checks, STARC, RMM, and Xilinx® UltraFast™ ◆ Design Methodology
◆ Use the GUI to streamline debug, integrated RTL schematics, and message viewer
◆ Use easy debug message sorting, filtering and waiving to pinpoint problems
◆ Automated flow with Tcl-based Command Line Interface (CLI), and re-usable message waiver file
Identify Design Issues Quickly
The Visual Verification Suite's Analyze RTL™ enables users to debug design issues quickly using intelligent sorting and message filtering.
◆ Low Noise
◆ Check customization for specific design style
◆ Easy setup
◆ Waiver migration
Finite State Machine Analysis
Rather than writing exhaustive simulation test benches to validate their finite state machines (FSMs), designers can use the FSM analysis capability within Analyze RTL™. With minimal effort, designers can:
◆ Extract FSMs from their RTL
◆ Find dead or unreachable states
◆ Generate easy to read bubble diagrams to better visualize FSMs
RTL Checks for High Speed Designs
It is important to find as early as possible RTL coding that prevents the design from getting desired speed. FPGAs, because of their more constrained fabric than ASIC, certain type of structures causes slow down. Rather than wait for synthesis or static timing analysis results, Analyze RTL™ users can easily identify:
◆ High fanout nets
◆ Deep nested"if-then-else"statements
◆ High levels of logic paths
◆ Reset methodology, Async/sync
The Blue Pearl Software Suite offers the capability to analyze and debug designs for Clock Domain Crossing (CDC) issues. Blue Pearl Software's Clock Domain Crossing Analysis solution comes with a complete set of CDC analyses, an Advanced Clock Environment (ACE) for solving the iterative and reactive CDC setup problem, and a comprehensive set of debugging tools.
◆ Reduces metastability by finding improper synchronizers or clock domain groupings
◆ Identifies CDC synchronization types
◆ Uses IP block modeling capability to reduce complexity and accommodates lack of model availability
◆ Provides reports and schematics to understand and debug CDC synchronization
◆ Easy setup by identifying clocks and FPGA clock generators
Why CDC Analysis
Today's designs routinely have millions of gates with memories, transceivers, third party IP and processor cores. They have a growing number of clocks that are asynchronous to each other. In order for data to transfer properly from one asynchronous clock domain to another, there needs to be a synchronizer to capture the data reliably and avoid metastability. With Blue Pearl's CDC Analysis tool, designers have access to:
◆ Analyzing CDCs from a GUI or in batch mode
◆ Easily run CDC analysis using different scenarios
◆ Easy setup with specific group checks
◆ Full Tcl parser to read in familiar inputs where clocks and domains have already been defined
◆ Identify synchronization issues between interacting clocks
Ease of Setup
By using ACE to visualize clocks and asynchronous clock domain crossings before running a CDC analysis, designers can clearly see if clocks are not in the intended domains and make corrections before in-depth CDC analysis.
◆ Blue Pearl helps ease the setup
◆ Automatic Clock and reset identification
◆ SDC input of Domain information
◆ Understands FPGA clock generator blocks to propagate clocks
◆ Advanced clock analysis diagram
CDC Analysis Types
◆ Missing synchronizers
◆ Re-converging nets
◆ Combinational logic in synchronizers
◆ Combinational logic before synchronizers
Understands FPGA vendor clock schemes
Most CDC tools do not understand FPGA vendor clocking schemes. Designers thus spend enormous resources to set up their designs. Blue Pearl’s CDC has built-in intelligence such that with minimal effort, designers can
◆ Set up their CDC run
◆ Debug using the built-in cross-probing and schematic display
◆ Generated clocks from FPGA IP clock distribution module are in the same domain. This eases setup and minimizes false CDCs.
Easy CDC analysis for IP-based designs
In a typical flow, designers have to black box their generated or non-synthesizable IPs. The resulting CDC analysis is incomplete and does not report many CDC issues that lead to metastability in the field. With Blue Pearl's User Grey Cell™ (UGC) methodology, CDC issues across boundary interfaces can be identified.
◆ Blue Pearl release contains FPGA vendor UGC models
◆ UGC easy to create from data book
The Blue Pearl Software Visual Verification Suite provides enhanced Lint, Debug, Clock Domain Crossing (CDC) and automated SDC generation flows to accelerate RTL Verification. The Management Dashboard delivers improved visibility to ASIC, FPGA and IP RTL design rule and CDC checks to better assess schedules, risk and overall design quality.
This standalone option to the Visual Verification Suite provides real-time visibility into RTL verification progress, run to run, providing graphical project reports that can be customized for documentation and design reviews. Reports highlight coverage, errors, warning and waivers for both Analyze RTL Linting and Clock Domain Crossing (CDC) solutions.
Management Dashboard Features
The Management Dashboard is built on top of the Visual Verification Suite’s industry standard SQL database. The tool monitors and logs messages, Clock Domain Crossings and waivers per run to provide real-time visibility into RTL verification progress.
Reports can be customized to omit or show errors, warnings, comments and info comments allowing managers and designers to quickly customize focused reports on areas of interest. The tool works for both interactive and batch runs making it useful for individuals as well as design teams working on multiple ASIC or FPGA system designs.
Graphs from the Management Dashboard are easily exported in Microsoft Office tools for inclusion into documentation and standard reports making it ideal for program updates and design reviews.
◆ Track verification progress day to day and run to run
○ Messages, CDCs and waivers per run
○ Track both interactive and batch runs
◆ Exports to Microsoft Word, Excel and PowerPoint
◆ Runs on both Windows and Linux operating systems
The Blue Pearl Software's Visual Verification Suite is the next generation EDA solution for ASIC, IP and FPGA verification that automates RTL analysis, CDC analysis, and SDC generation. The Suite augments existing EDA and FPGA vendor tool flows with a native Windows or Linux user experience.
Today's designs routinely have millions of gates with memories, transceivers, third party IP and processor cores. They are too complex to debug in the lab. As a result, designers need verification tools that run before simulation, before synthesis, and definitely before programming chips in the lab.
ASICs and FPGAs have many false paths and multi-cycle paths that implementation tools attempt to optimize to meet timing goals. These paths can cause the critical paths to miss timing and waste run time and system memory. Adding false path constraints frees up the synthesis tool to work only on necessary paths that will give better results for a design.
Blue Pearl offers a way to automate false path generation that can be run after design changes.
Efficient Timing Exception Generation
In a typical design, there may be a significant number of false paths or multi cycle paths. Passing all of them to synthesis or place & route can be very expensive and taxing to these tools. Blue Pearl's efficient SDC generation:
◆ Limits the number of exceptions generated
◆ Reads in critical path information
◆ Accepts multiple formats
Targeted False Path and Multi Cycle Path Constraints
There are many more false paths in a design than implementation tools can effectively use. When input as timing exception constraints, implementation tools will often use excessive memory, runtime or ignore constraints beyond some number. Blue Pearl has the ability to accept critical path timing reports from Vivado and Quartus to identify select areas of the design and generate only the most critical false path constraints.
Tool Specific SDC Generated
Even though SDC is a standard format, every tool reads in a slightly different variant. This can limit what the tools actually process. Blue Pearl's SDC
◆ Generates tool-specific SDC variants
◆ Understands the synthesis name translation
◆ Easily plugs into existing flows
Multi-cycle Path Generation
Muti-cycle paths (MCPs) are important timing constraints to be specified for a design. If not included it may be difficult or impossible for these paths to meet timing. Blue Pearl has the ability to find MCPs in the design and generate SDC constraints. Blue Pearl will also indicate where within the RTL code the MCP is in the design and a schematic representation to help visualize the path.
Intelligent SDC Compare
Designers perform several iterations before they close timing. It is thus important to have a mechanism to quickly compare results between runs. Blue Pearl's SDC Compare is:
◆ Easy to use
◆ Provides an intelligent mechanism to track changes
◆ Is integrated with the Visual Verification Environment™
Blue Pearl Software's ACE offers the capability to visualize clocks and asynchronous clock domain crossings in RTL designs to help users analyze their design for CDC metastability.
The Advanced Clock Environment (ACE) tool solves the iterative and reactive CDC setup problem experienced by designers. It is used before running a CDC analysis. With ACE, designers can clearly see if clocks are not in the intended domains and make corrections before in-depth CDC analysis.
What is ACE?
Blue Pearl Software's Advanced Clock Environment provides a graphical representation summarizing data paths between clocks and can make recommendations for grouping of clocks into clock domains. With ACE, designers can identify clocks to better understand how they interact with synchronizers in the design. This allows users to quickly identify improper synchronizers or clock domain groupings that cause CDC metastability.
Why should I be concerned with metastability and CDC?
At its most basic level, metastability is what happens within a register when data changes too soon before or after the active clock edge; that is, when setup or hold times are violated. A register in a metastable state is in between valid logic states, and the process of settling to a valid logic state takes much longer than normal. It will eventually fall into a stable "1" or "0" state, but there is no way to predict which way it will fall or how long it will take. If the metastable state lasts longer than one clock cycle, it can be transferred to the next register.
When data is transferred between two registers whose clocks are asynchronous, metastability will happen. There is no way to prevent it. All you can do is to minimize its impact by placing the two clocks in different clock domains and using a clock synchronization technique at the crossing point. Hence the name "clock domain crossing" (CDC).
Putting two clocks into the same clock domain is a declaration that these two clocks are synchronous to each other, and CDCs between them do not need to be synchronized. If the clocks are from the same source, or one is derived from the other, then they are synchronous and should be placed into the same clock domain.
Clocks that are asynchronous to one another should always be placed in different clock domains, and any CDCs between them should be synchronized. Even two clocks of the same frequency should be placed into different domains if they come from independent sources. All specifications have tolerances or "error bars," and two independent clock sources of the same frequency will drift relative to one another over time. Failing to synchronize CDCs between two such clocks will cause metastability problems.
What can I do with ACE?
◆ Evaluate clock domain definitions
◆ Evaluate SDC clock constraints
◆ Generate a graphical analysis of clock and clock domains
◆ Validate clock grouping recommendations
◆ Generate SDC template to be used by a CDC analysis tool
Features of ACE
◆ Detailed analysis of clock, clock groupings, and interactions
◆ Visual display filters enable quick debug
◆ Pinpoint exact location of problem in RTL design
Why should I use ACE?
Without proper clock domain setup, CDC analysis results are unreliable.
Virtually impossible for any tool to automatically deduce all the clock domains
Designers perform many CDC iterations as they incrementally make clock/clock domain decisions
The overall goal of Advanced Clock Environment is to enable engineers to find metastability issues in designs by properly grouping clocks into clock domains. Design and Verification engineers use ACE to ensure the clock domains are properly specified before running a CDC analysis.
ACE will quickly find errors in clock domain groupings, or find/recommend appropriate clock domain groupings for a circuit that is synchronized.
Engineers who are interested in reducing cycle times, by identifying problems early on, find Blue Pearl's Advanced Clock Environment a great addition to their existing design environment.
Blue Pearl Software, Inc. provides products that check digital design issues at the functional or register transfer level (RTL) of the chip design flow. These issues include clock domain crossings (CDCs), synthesis vs. simulation mismatches, inadvertent latch generation, coding style and conventions, and basic linting, as well as verifying conformance with design standards such as DO-254, STARC, and RMM. Blue Pearl’s software is used by ASIC and FPGA designers early in the design flow on high-level functional design descriptions of an integrated circuit (IC), to develop higher quality RTL code, and can also automatically generate comprehensive and accurate timing constraints that significantly improve quality of results (QoR). Our customers can significantly reduce time to market, lower design costs, and make the design development schedule more predictable. Incorporating Blue Pearl’s products in the design flow is easy as all inputs and outputs are industry standards.