Blue Pearl Software’s ACE offers the capability to visualize clocks and asynchronous clock domain crossings in RTL designs to help users analyze their design for CDC metastability. The Advanced Clock Environment (ACE) tool solves the iterative and reactive CDC setup problem experienced by designers. It is used before running a CDC analysis. With ACE, designers can clearly see if clocks are not in the intended domains and make corrections before in-depth CDC analysis. Blue Pearl Software’s Advanced Clock Environment provides a graphical representation summarizing data paths between clocks, and can make recommendations for grouping of clocks into clock domains. With ACE, designers can identify clocks to better understand how they interact with synchronizers in the design. This allows users to quickly identify improper synchronizers or clock domain groupings that cause CDC metastability. Using the the advanced clock environment (ACE) tool, designers can evaluate clock domain definitions; evaluate SDC clock constraints; generate a graphical analysis of clock and clock domains; validate clock grouping recommendations; generate SDC template to be used by a CDC analysis tool.

ASICs and FPGAs have many false paths and multi-cycle paths that implementation tools attempt to optimize to make timing goals. These paths can cause the critical paths to miss timing, and waste run time and system memory. Adding false path constraints frees up the synthesis tool to work only on necessary paths that will give better results for a design. Blue Pearl offers a way to automate false path generation that can be run after design changes. In a typical design, there may be a significant number of false paths or multi cycle paths. Passing all of them to synthesis or place & route can be very expensive and taxing to these tools. Blue Pearl’s smart SDC generation limits the number of exceptions generated, reads in critical paths information and accepts multiple formats. There are two main benefits of SDC generation, one is accelerating timing closure. Blue Pearl’s SDC will automatically find the timing exceptions, that is, the false paths and multi cycle paths, and provide that information to the implementation tools. Other features that help with timing closure are max fanout checks, if-then-else depth and longest path capability. The other benefit is finding the exceptions that matter. There are many more false paths in a design than implementation tools can effectively use. When input as timing exception constraints, implementation tools will often use excessive memory, runtime or ignore constraints beyond some number. Blue Pearl has the ability to input critical path timing reports from static timing analysis tools, identifying select areas of the design generating false paths.

Guarantee high reliability RTL with the Visual Verification Suite Management Dashboard. The Blue Pearl Management Dashboard delivers real-time visibility to ASIC, FPGA and IP RTL design rule and CDC checks to better assess schedules, risk and overall design quality. This standalone option to the Visual Verification Suite, provides RTL Designers, Verification Engineers and Managers visual insight into the RTL verification progress, run to run, providing graphical reports on the number of fixed and outstanding Messages, Clock Domain Crossing issues and Waivers. The Design Sign off dashboard can be customized to ensure the code has been analyzed and has passed all user defined mandatory checks. These graphical reports, generated for both GUI and Tcl flows, can be customized and exported for use in documentation and design reviews. This standalone option to the Visual Verification Suite provides real-time visibility into RTL verification progress, run to run, providing graphical project reports that can be customized for documentation and design reviews. Reports highlight coverage, errors, warning and waivers for both Analyze RTL Linting and Clock Domain Crossing (CDC) solutions. The following 5 features makes management dashboard an ideal tool for designers: Monitors and logs messages, Clock Domain Crossings and Waivers day to day and per run to provide real-time visibility into the RTL verification progress; Customize report to omit or show errors, warnings, comments and information; Works for both interactive and batch runs, making it useful for individual system designs; Easily exported in Microsoft Office tools for inclusion into documentation and standard reports, making it ideal for program updates and design reviews; Runs on both Windows and Linux operating systems.

Todays designs routinely have millions of gates with memories, transceivers, third party IP and processor cores. They have a growing number of clocks that are asynchronous to each other. In order for data to transfer properly from one asynchronous clock domain to another, there needs to be a synchronizer to capture the data reliably and avoid metastability. The Blue Pearl Software Suite offers the capability to analyze and debug designs for Clock Domain Crossing (CDC) issues. Blue Pearl Software’s Clock Domain Crossing Analysis solution comes with a complete set of CDC analyses, an Advanced Clock Environment (ACE) for solving the iterative and reactive CDC setup problem, and a comprehensive set of debugging tools. The Blue Pearl Software Suite offers the capability to analyze ASIC and FPGA designs for Clock Domain Crossing (CDC) issues: Finds places in design that don’t have CDC synchronization that cause metastability; Identifies CDC synchronization types; Has IP block modeling capability that reduces complexity and accommodates lack of model availability; Has reports and schematic to understand and debug CDC synchronization; Easy setup by identifying clocks and FPGA clock generators; CDC is an option to Analyze RTL™, the base product within the software suite. Blue Pearl eases design set up with automatic Clock and reset identification, SDC input of Domain information, understanding of clock generator blocks to propagate clocks and our advanced clock interaction diagram.

Modern ASICs, SoCs and FPGAs routinely have millions of gates with memories, transceivers, third party IP and processor cores. RTL issues can be time consuming and complex to debug in the lab and through simulations. To reduce verification and debug times, designers need tools that can identify problems quickly before simulation and synthesis, and definitely before spending time in the lab. The Blue Pearl Software Visual Verification Suite provides enhanced Lint, Debug, Clock Domain Crossing (CDC) and automated SDC generation flows to accelerate RTL Verification. Analyze RTL™ provides RTL linting combined with a powerful debug environment with the industry’s fastest bug find/fix rate to quickly identify critical design issues, up front, streamlining simulation and synthesis while improving overall quality of results. The Visual Verification Environment enables Analyze RTL™ users to debug design issues quickly using intelligent sorting and message filtering. The key features include low Noise, check customization for specific design style, easy setup, and waiver migration. Blue Pearl’s Analyze RTL™ combines the ease-of-use methodology and extensive analysis of super-lint tools with the power of formal verification into a single high performance, high capacity design checking solution. With Blue Pearl, you get a unique combination of powerful built-in checks and formal analysis that gives you the most comprehensive and powerful static design checking capability available. Deploy Blue Pearl early and eliminate complex design errors at all stages of your design implementation cycle and drastically reduce the amount of effort you spend finding bugs later using time-consuming traditional test-bench methods.

VeriTiger®-K115 is a pretty agile and easy bring-up prototyping system from HyperSilicon, using Xilinx Kintex UltraScale XCKU115 FPGA. VeriTiger®-K115 delivers high performance, fast running speed and flexible scalability to accelerate software development, system verification and validation. Through the Protowizard® software to manage prototyping runtime resource and Semu® software to deliver highest debug productivity, VeriTiger®-K115 can significantly reduce the digital IC development time.

VeriTiger®-V9P is a pretty agile and easy bring-up prototyping system from HyperSilicon, using Xilinx Virtex UltraScale+ XCVU9P FPGA. VeriTiger®-V9P delivers high performance, fast running speed and flexible scalability to accelerate software development, system verification and validation. Through the Protowizard® software to manage prototyping runtime resource and Semu® software to deliver highest debug productivity, VeriTiger®-V9P can significantly reduce the digital IC development time.

VeriTiger®-V13P is a pretty agile and easy bring-up prototyping system from HyperSilicon, using Xilinx Virtex UltraScale+ XCVU13P FPGA. VeriTiger®-V13P delivers high performance, fast running speed and flexible scalability to accelerate software development, system verification and validation. Through the Protowizard® software to manage prototyping runtime resource and Semu® software to deliver highest debug productivity, VeriTiger®-V13P can significantly reduce the digital IC development time.

VeriTiger®-E4000T Series is the most deployed prototyping system from HyperSilicon, using Xilinx Virtex UltraScale XCVU440 FPGA, which is the industry’s only high-end FPGA at the 20nm process node. VeriTiger®-E4000T Series delivers high performance, fast running speed and flexible scalability to accelerate software development, system verification and validation. Through the Protowizard® software to manage prototyping runtime resource and Semu® software to deliver highest debug productivity, VeriTiger®-E4000T Series can dramatically reduce the time-to-tapeout (TTT) pressure of digital IC design.

We also provide professional SoC design service, include: Frontend design Backend design，Turnkey and MPW.