Modern ASICs, SoCs and FPGAs routinely have millions of gates with memories, transceivers, third party IP and processor cores. RTL issues can be time consuming and complex to debug in the lab and through simulations. To reduce verification and debug times, designers need tools that can identify problems quickly before simulation and synthesis, and definitely before spending time in the lab. The Blue Pearl Software Visual Verification Suite provides enhanced Lint, Debug, Clock Domain Crossing (CDC) and automated SDC generation flows to accelerate RTL Verification. Analyze RTL™ provides RTL linting combined with a powerful debug environment with the industry’s fastest bug find/fix rate to quickly identify critical design issues, up front, streamlining simulation and synthesis while improving overall quality of results. The Visual Verification Environment enables Analyze RTL™ users to debug design issues quickly using intelligent sorting and message filtering. The key features include low Noise, check customization for specific design style, easy setup, and waiver migration.
Blue Pearl’s Analyze RTL™ combines the ease-of-use methodology and extensive analysis of super-lint tools with the power of formal verification into a single high performance, high capacity design checking solution. With Blue Pearl, you get a unique combination of powerful built-in checks and formal analysis that gives you the most comprehensive and powerful static design checking capability available. Deploy Blue Pearl early and eliminate complex design errors at all stages of your design implementation cycle and drastically reduce the amount of effort you spend finding bugs later using time-consuming traditional test-bench methods.